"filename ~munro/vl/babar/format.abl "Major changes "xx June 97 > xxxx. "Description of state machine "This controls the tristate enables from the shift registers "of the formatter to it's buffer register "when read event occurs "BUGS TO FIX "Design still to do "Inform Software people to check the mask has no zero columns module format title '???????' declarations "LIST OF INPUTS m0..m8 pin; "sync ram mask output clk pin; "system clock 59.5MHz (CLK60) next_mask_valid pin; "from daq.abl: sync ram mask output valid shift_data_valid pin; "from daq.abl: shift reg has shifted all 16 bits all_daq_read pin; "from daq.abl: all daq event data has been read start_readout pin; "from daq.abl: start_readout at start of read event load_top_stream pin; "from streamer, used to show first data loaded bot_shift pin; "from streamer, used to show buffer can be reloaded "LIST OF OUTPUTS "USE -> pin istype 'reg_d, buffer'; "so that outputs are registered to avoid glitches "See further notes on output sets below. !_oe0..!_oe8 pin istype 'reg_d, buffer'; "enables shift output to longlines next_frame pin istype 'reg_d, buffer'; "to daq.abl buffer_ce pin istype 'reg_d, buffer'; "to formatter's buffer reg !_oe_header pin istype 'reg_d, buffer'; "enables header output to longlines dis_daq_shift pin istype 'reg_d, buffer'; "to stream control "ADD new outputs to pos/neg_set below "LIST OF NODES q0..q8 node istype 'reg_d, buffer'; "stores mask from ram header_flag node istype 'reg_d, buffer'; "flags when header sent "ADD new nodes to node_set below "**** WHEN ALTERING OR ADDING AN active high OUTPUT **************************** "i) add its pin definition above "ii) add to pos_set below to define its clock and reset inputs "iii) define in state_diagram OR .. " define by equation in terms of set and reset states, " (see examples below) "WHEN ALTERING OR ADDING AN active low OUTPUT "i) add its pin definition above - define as !output "ii) add to neg_set below to define its clock and reset inputs "iii) define in state_diagram OR .. " define by equation in terms of set and reset states, " if defining by set/reset equation use !output.q equation " (see examples below) " NB: output:=1; MEANS output:=active => pin level will be low "******************************************************************************* "state declarations and assignments "define variable sets for .clk and .ar definitions pos_set1 = [next_frame, buffer_ce]; pos_set2 = []; pos_set3 = []; pos_set4 = []; pos_set = [pos_set1, pos_set2, pos_set3, pos_set4]; neg_set = [_oe0.._oe8, _oe_header, dis_daq_shift]; node_set = [q0..q8, header_flag]; reg_set = [pos_set, neg_set, node_set]; "for .clk later "intermediate expressions mask_reg = [q0..q8]; "state definitions for symbolic one hot encoding "see XABEL USER GUIDE format state_register istype 'reg_D'; "**** DEFINE STATES ************************************************************ wait_start, start_readout1, load_header1, load_header2, load_header3, load_buffer1, load_buffer2, wait_mask_latched1, wait_mask_latched2, next_column1, next_column2, next_column3, next_frame1, tri_header1, tri0, tri1, tri2, tri3, tri4, tri5, tri6, tri7, tri8, gsr_state state; "******************************************************************************* "define the power up and global reset state.. xilinx property 'Initialstate gsr_state'; "If changing this state change also the async line "just after the state_diagram definition. equations "**** FOR HIGH SPEED STATE MACHINES ****************************************** "define outputs set and reset states as follows "output.d = output.q & !(reset states) # (set states); "note that set is domimant if both set and reset conditions are both true "e.g. test.d = test.q & !(up_loop1 # up_loop6) # (up_loop4 # up_loop6); "DO NOT USE 'DCSET' as this could alter some output equations "logic should fit into F,G,H maps (set and reset states will be the inputs) "Maximum no. of levels should be 2 to ensure 60MHz operation in Xilinx 4000E "UPDATE THESE EQUATIONS WHEN STATE MACHINE CHANGED "output.d = output.q & !(reset states) # (set states); "***************************************************************************** header_flag.d = header_flag.q & !(tri_header1) # (start_readout1); dis_daq_shift.d = dis_daq_shift.q & !(load_header3) # (wait_start); "***************************************************************************** "ACTIVE LOW definitions are as follows (due to the .ap input) "[To see why refer to fig 4-6 p4-13 Xilinx ABEL USER GUIDE April 1994] "output.d = !output.q & !(states where output turned active) " # (states where output turned inactive); "***************************************************************************** "***************************************************************************** "All other outputs are defined in state diagram "GLOBAL FLIP FLOP CONTROLS format.clk=clk; "all state variables triggerred by clk reg_set.clk=clk; "all register bits triggerred by clk pos_set.ar=0; "active high outputs reset by state reset neg_set.ap=0; "active low outputs set by state reset mask_reg.d = [m0..m8]; "load from mask inputs using .ce later " now define the state machine ************************************************* state_diagram format "Use the following if using a sync_reset or async_reset input "sync_reset gsr_state: st_reset; state gsr_state: "the power up and reset state "output values here will be "pos_set:=^b0; 0 for all pos_set outputs "neg_set:=^b-1; 1 for all neg_set outputs goto wait_start; " wait_start state ************************************************************* state wait_start: "the wait_start state "set dis_daq_shift in equations - This will disable the daq streamer if (start_readout) then goto start_readout1 else goto wait_start; state start_readout1: "set header_flag in equations - flag used to ensure first mask gets loaded if (next_mask_valid) then goto wait_mask_latched1 "await first mask valid else goto start_readout1; " wait_mask_latched1 state ***************************************************** state wait_mask_latched1: " mask_reg.ce:=1; " goto wait_mask_latched2; state wait_mask_latched2: "Extra state ensures mask output ready for next_column1 goto next_column1; " next_column states ******************************************************** state next_column1: "several next_column states give a faster clock speed if (header_flag) then goto tri_header1 else if (q0) then goto tri0 else if (q1) then goto tri1 else if (q2) then goto tri2 else goto next_column2; state next_column2: "several next_column states give a faster clock speed if (q3) then goto tri3 else if (q4) then goto tri4 else if (q5) then goto tri5 else goto next_column3; state next_column3: "several next_column states give a faster clock speed if (q6) then goto tri6 else if (q7) then goto tri7 else if (q8) then goto tri8 else goto next_frame1; "no remaining bits are set " tristate enables ******************************************************** state tri_header1: "Put header on longlines _oe_header:=1; "activate data onto longlines to buffer input "reset header_flag in equations - clear the bit now that it's been used if (_oe_header) then goto load_header1 "await longline data valid else goto tri_header1; state tri0: " _oe0:=1; "activate data onto longlines to buffer input q0.sr=1; "clear the bit now that it's been used if (_oe0 & shift_data_valid) then goto load_buffer1 "await longline data valid else goto tri0; state tri1: " _oe1:=1; "activate data onto longlines to buffer input q1.sr=1; "clear the bit now that it's been used if (_oe1 & shift_data_valid) then goto load_buffer1 "await longline data valid else goto tri1; state tri2: " _oe2:=1; "activate data onto longlines to buffer input q2.sr=1; "clear the bit now that it's been used if (_oe2 & shift_data_valid) then goto load_buffer1 "await longline data valid else goto tri2; state tri3: " _oe3:=1; "activate data onto longlines to buffer input q3.sr=1; "clear the bit now that it's been used if (_oe3 & shift_data_valid) then goto load_buffer1 "await longline data valid else goto tri3; state tri4: " _oe4:=1; "activate data onto longlines to buffer input q4.sr=1; "clear the bit now that it's been used if (_oe4 & shift_data_valid) then goto load_buffer1 "await longline data valid else goto tri4; state tri5: " _oe5:=1; "activate data onto longlines to buffer input q5.sr=1; "clear the bit now that it's been used if (_oe5 & shift_data_valid) then goto load_buffer1 "await longline data valid else goto tri5; state tri6: " _oe6:=1; "activate data onto longlines to buffer input q6.sr=1; "clear the bit now that it's been used if (_oe6 & shift_data_valid) then goto load_buffer1 "await longline data valid else goto tri6; state tri7: " _oe7:=1; "activate data onto longlines to buffer input q7.sr=1; "clear the bit now that it's been used if (_oe7 & shift_data_valid) then goto load_buffer1 "await longline data valid else goto tri7; state tri8: " _oe8:=1; "activate data onto longlines to buffer input q8.sr=1; "clear the bit now that it's been used if (_oe8 & shift_data_valid) then goto load_buffer1 "await longline data valid else goto tri8; " loading buffer ************************************************************** " **** 1st pass **** load buffer then wait start of streamer state load_header1: "header data valid at buffer reg input buffer_ce:=1; "load buffer - this signals to stream.abl goto load_header2; state load_header2: "wait for top_stream to load for first time if (load_top_stream) then goto load_header3 "wait first load else goto load_header2; state load_header3: "top_stream now loaded - start the shifting "reset dis_daq_shift in equations - This will start the shift register streamers goto next_column1; "return to normal flow " *** other passes *** load buffer after contents copied state load_buffer1: "data will now be valid at buffer reg input if (bot_shift) then goto load_buffer2 "this implies both streams loaded else goto load_buffer1; state load_buffer2: "now load the buffer buffer_ce:=1; goto next_column1; "fetch next data " next_frame1 state *********************************************************** state next_frame1: " next_frame:=1; if (next_mask_valid) then goto wait_mask_latched1 else if (all_daq_read) then goto wait_start else goto next_frame1; " *********************** end of state machine ************************* "No ABEL test vectors - will use Viewsim instead end