VME Address Map for EMC Trigger                     27/05/98
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The VME base address for each TPB is constructed from a header hardwired
on each board and the geometrical address which is obtained from the custom
J3 backplane and so differs for each board. The footprint of each board is
128 16-bit words.

The A24 base address bits are constructed as follows;
  A16-A23   Hardwired header (set to the same value for all TPB's = 0xff)
  A12-A15   Zero
  A08-A11   Geometric address (0-9 for the 10 TPB's)
  A00-A07   TPB internal addresses
Hence, each board will be distinguished by the geometric address only.

The internal addresses all perform read-only access to 16-bit words, with
16-bit transfers only. The board space addresses used are
  Base Address+ 0   Algorithm Xilinx 0 Spy FIFO AB
  Base Address+ 2   Algorithm Xilinx 0 Spy FIFO CD
  Base Address+ 4   Algorithm Xilinx 1 Spy FIFO AB
  Base Address+ 6   Algorithm Xilinx 1 Spy FIFO CD
  Base Address+ 8   Algorithm Xilinx 2 Spy FIFO AB
  Base Address+10   Algorithm Xilinx 2 Spy FIFO CD
  Base Address+12   Algorithm Xilinx 3 Spy FIFO AB
  Base Address+14   Algorithm Xilinx 3 Spy FIFO CD
  Base Address+40   Control and status register
  Base Address+42   Cable errors register
  Base Address+44   Other errors, geometric address and serial number
All other addresses within the board footprint should not be used. Note,
the spy FIFO data are read out sequentially by multiple reads from the
same address location.